tag:blogger.com,1999:blog-5560209661389175529.post5980356954194735688..comments2021-11-26T19:34:10.855+00:00Comments on Mechanical Sympathy: Processor Affinity - Part 1Martin Thompsonhttp://www.blogger.com/profile/15893849163924476586noreply@blogger.comBlogger19125tag:blogger.com,1999:blog-5560209661389175529.post-33441338747533687142016-12-23T09:20:44.581+00:002016-12-23T09:20:44.581+00:00This comment has been removed by the author.shahttps://www.blogger.com/profile/01575551063915562862noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-42179736228252274822016-12-21T09:59:08.663+00:002016-12-21T09:59:08.663+00:00Google code has been archived so I moved them to G...Google code has been archived so I moved them to GitHub.Martin Thompsonhttps://www.blogger.com/profile/15893849163924476586noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-41126820079848434782016-12-20T05:51:22.264+00:002016-12-20T05:51:22.264+00:00Hi Martin,
The links to source code (Sender and ...Hi Martin, <br /><br />The links to source code (Sender and Receiver) is broken.<br />Could you please update them?<br />shahttps://www.blogger.com/profile/01575551063915562862noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-52392719781954048472016-11-18T12:50:19.168+00:002016-11-18T12:50:19.168+00:00Hi, great article, thx!
Is there part II released?...Hi, great article, thx!<br />Is there part II released? It sounds like you were to describe some interesting stuff - interrupt handling.<br />Cheers, <br />MichaĆ<br />stachuhttps://www.blogger.com/profile/06445299835723324553noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-69188434095023731772016-09-24T01:45:39.419+01:002016-09-24T01:45:39.419+01:00No simple answer here. You need to consider contro...No simple answer here. You need to consider control groups, isocpus, and other config options.Martin Thompsonhttps://www.blogger.com/profile/15893849163924476586noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-64567665951785808752016-09-23T13:17:51.710+01:002016-09-23T13:17:51.710+01:00Hi Martin,
How will this work if a process has mo...Hi Martin,<br /><br />How will this work if a process has more than one thread? Will it pin all threads or will it pin only the main thread?Ivan Mushketykhttps://www.blogger.com/profile/02170717132764703938noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-35560900066693426372014-11-19T06:52:28.028+00:002014-11-19T06:52:28.028+00:00Thanks, I tried running the java with dummy0 but t...Thanks, I tried running the java with dummy0 but the receive did not receive anything, even though I turned off selinux. But after I changed to lo it all worked, thanks.Alex Lamhttps://www.blogger.com/profile/11042157787558492996noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-51379149043018668892014-11-17T12:56:46.121+00:002014-11-17T12:56:46.121+00:00Should be fine if the you are connected to a netwo...Should be fine if the you are connected to a network. Dummy works well even if a network is not connected.Martin Thompsonhttps://www.blogger.com/profile/15893849163924476586noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-90953644624369241802014-11-17T07:14:56.299+00:002014-11-17T07:14:56.299+00:00Hi,
For the dummy interface part, can I just use...Hi, <br /><br />For the dummy interface part, can I just use lo interface and 127.0.0.1 instead?<br /><br />AlexAlex Lamhttps://www.blogger.com/profile/11042157787558492996noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-8372421679665079472012-03-29T18:07:39.419+01:002012-03-29T18:07:39.419+01:00Use the model specific registers (MSRs) for your C...Use the model specific registers (MSRs) for your CPU to get all the data you need on how the process is executing. Cheap way is "perf stat" on Linux. I have seen the OS schedule the thread to execute on another core too readily. This is worst with Linux; Windows, BSD and OSX do much better. Being scheduled to another core is even worse than having another thread partially pollute your warm cache.<br /><br />If you have other threads running on that core it can cause the cache pollution as you point out. For low-latency applications you do not want to have this happen. This may mean you are over-provisioning cores.Martin Thompsonhttps://www.blogger.com/profile/15893849163924476586noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-61776828940117107542012-03-29T17:45:44.843+01:002012-03-29T17:45:44.843+01:00You have observational evidence that pinning helps...You have observational evidence that pinning helps which is good but you assign the cause as being accumulated processor state. How did you reach that conclusion? <br /><br />I base that question on the following - when the next thread is scheduled to run all the processor registers, cache-lines etc. will be loaded for that thread effectively flushing all your currents threads state (indeed the OS should save all that state for you). This will continue for subsequent threads until your thread is re-scheduled to run on that processor.<br /><br />Regards,<br />MattAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-61240993572573296362011-11-28T19:41:00.075+00:002011-11-28T19:41:00.075+00:00Martin, this is a great post.
You finish by menti...Martin, this is a great post.<br /><br />You finish by mentioning "In the next article of this series [...]". And as the title suggest, there should be a Part 2. Where is it? Eagerly waiting for it.<br /><br />Continue the great work!Smartdreamerhttps://www.blogger.com/profile/04064105467710227469noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-4016347434461329722011-07-29T06:56:47.077+01:002011-07-29T06:56:47.077+01:00Dedicating a CPU for interrupt handling can be a v...Dedicating a CPU for interrupt handling can be a very valid technique for certain types of workload. It is one of the points I plan to cover in the next instalment of this series.Martin Thompsonhttps://www.blogger.com/profile/15893849163924476586noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-2161008119079920412011-07-29T03:26:34.835+01:002011-07-29T03:26:34.835+01:00How about processor affinity for interruptions? Do...How about processor affinity for interruptions? Do you think if it is good practice to dedicate one cpu for interruption handling?Xin Wanghttps://www.blogger.com/profile/10838263726856922649noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-86927813517929368362011-07-20T19:15:17.494+01:002011-07-20T19:15:17.494+01:00i've used taskset in the past to pin init and ...i've used taskset in the past to pin init and everything under it to one core and then have my "soft-realtime" processes pinned to the other cores on the box. this way the OS shouldn't interfere with any of your application processes. Idea is to always have at least one core dedicated to the OS. Linux containers and cgroups are also well worth investigating...billywhizzhttps://www.blogger.com/profile/12164174598577012452noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-8945988549298864512011-07-20T07:27:50.671+01:002011-07-20T07:27:50.671+01:00taskset is the cheap and cheerful means of setting...taskset is the cheap and cheerful means of setting affinity. Other means exist such as cgroups which can be used to contain OS threads for avoiding contention with the cores assigned to specific tasks. I used taskset for quick illustration of what is possible.Martin Thompsonhttps://www.blogger.com/profile/15893849163924476586noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-14162213595224446142011-07-20T07:24:16.453+01:002011-07-20T07:24:16.453+01:00When sharing the same L2 cache I'm assuming yo...When sharing the same L2 cache I'm assuming you are using a pre-Nehalem Intel processor such as Penryn? If so, you are seeing the benefits of exchanging data via the L2 rather than the L3 cache as in my test. This will obviously be faster between two cores but does not scale to more cores as well as the Nehalem processors do. Most processors now operate a 3 layer cache with only the third level shared if you discount hyper threading.Martin Thompsonhttps://www.blogger.com/profile/15893849163924476586noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-48061140097024595982011-07-20T00:26:12.972+01:002011-07-20T00:26:12.972+01:00Hi Martin.
No doubt you will already have this in...Hi Martin.<br /><br />No doubt you will already have this in mind for a future post, but I am curious about what sort of constraints you may have in place for ensuring that other threads are not utilising the resources of the CPUs that the sender and receiver processes (obviously single-threaded) have affinity to.Stephen Sounesshttps://www.blogger.com/profile/02865488454850253029noreply@blogger.comtag:blogger.com,1999:blog-5560209661389175529.post-42096641935678298502011-07-19T23:24:04.944+01:002011-07-19T23:24:04.944+01:00i see the same results here. also, if you make sur...i see the same results here. also, if you make sure to pin the two processes to cores that share the same L2 cache you get double the throughput over two cores on different L2 caches. I presume this is the overhead of the cache interconnect?billywhizzhttps://www.blogger.com/profile/12164174598577012452noreply@blogger.com